1. Field of Use
The present invention relates generally to data processing systems and more precisely to multiprocessor systems which use standard system busses for interprocessor communication.
2. Prior Art
In modern data processing systems, the trend is well developed of using communication busses and components (memory units, processors, peripheral unit controllers, all implemented as printed circuit boards) of standard type. This is advisable in order to limit the design and development activity to specific components and integrating the system architecture with a plurality of components already available on the market, so as to make readily available to customers products which are flexible and suitable to the several user needs with a limited incidence of development costs on the product costs.
Electronic components implemented in a single printed circuit board (PCB) and interfacing with either one or the other of two standard system busses are wide spread in the market.
A first standard bus is known by the name VME bus and is defined by specifications published in 1982.
A second standard bus is known by the name MULTIBUS II or PSB, in the following referenced as PSB, and is defined by specifications published in 1987 by IEEE with code P1296 PSB Standard.
The two busses differ in several respects.
The VME bus is of asynchronous type, and has distinct channels for data and addresses.
The PSB bus is of synchronous type, with a single channel which is used for transferring both addresses and data in different time phases. The communication protocols are quite different and the PSB bus offers direct interprocessor communication capability which is not provided by the VME bus. Therefore, it is particularly suitable as system bus for a multiprocessor system where a plurality of central processing units (CPU's) share the tasks.
The VME bus is more suitable in system where a plurality of I/O processors or peripheral unit controllers have to communicate with a single central processing unit (in case of a plurality of CPUs, the several CPUs must communicate each with the other in an indirect way, through "mailboxing" procedures).
For these reasons a multiplicity of standard boards is available on the market, which boards have an interface for connection to the VME bus and perform the function of controllers for peripheral units of many various kinds.
Because more expensive, there is not at present on the market a corresponding variety of standard boards having an interface for connection to the PSB bus.
Therefore, it is desirable to have instruments which enable combining the two worlds, that is to use control boards having VME interface in a multiprocessor environment where the PSB bus is used.
To meet this need, it has been proposed to design system architectures where both kind of busses are present and connected together through complex equipments or "gateways", an example of which is described in the European Patent Application EP-A-0260392, of Feb. 23, 1988.
The function of these "gateways" is to adapt the communication protocol used in the VME bus to the one used in the PSB bus and vice versa, so as to enable information exchange between the two busses.
From the architectural standpoint the use of gateways implies the design of systems comprising two distinct structural blocks: a VME environment connected to a VME bus and a PSB environment, connected to a PSB bus.
The two blocks communicate each with the other through one or more intercommunication boards which constitute the gateway.
This arrangement is rigid: the mechanical and electrical implementation of the systems requires the implementation of the two busses on one or two "backpanels" to which several printed circuit boards are connected through connectors.
If the system is designed to connect a maximum number M of boards to the VME bus and a maximum number N of PSB boards to the PSB bus for a total of M+N boards, it is impossible to configure systems where more than M VME boards are present, or more than N PSB boards.
In addition the gateway mechanism is a cause of performance degradation, because a double arbitration is required for access to the bus.
The two arbitrations cannot be time overlapped.
For example, the processors connected to the VME bus must first obtain access to the VME bus with an arbitration operation. Once obtained, they must obtain access to the PSB bus through the gateway, with a second arbitration. Conflicts may occur, which may be solved by retry procedure only, in case access is requested from VME bus to the PSB bus and at the same time access is requested from PSB bus to the VME bus.